x86 is harder to decode than arm since the instructions are anywhere between 1-15 bytes while arm instructions are 4 bytes each. It has quite an effect if you want to decode more than 1 instruction per cycle.
x86 has a stronger memory model than arm, which will come at an extra cost if implementing any sort of out-of-order execution. I'm not very familiar with how it affects the cache implementation.
The x86 instruction set is more complicated than arm, and instructions frequently decode into multiple uops. I believe that microcode is used more extensively in x86.
I wonder how much that has to do with Intel being a node size ahead of the pack. That said, i know they have been trying to get away from the notion of TDP in recent years because they design their CPUs around the concept of "race to idle". In other words that they try to save power by getting things done ASAP and then put the CPU to sleep until there is input from the user or similar.
intel botched their integration, ISA is a tiny tiny part of that. ARM solutions were designed for IP integration from the start by necessity of ARM being an IP provider instead of a whole package provider, so customers were free to create their own chips that contained everything required at a few (dozen or w/e) dollars less than intel was able to offer.
x86 is harder to decode than arm since the instructions are anywhere between 1-15 bytes while arm instructions are 4 bytes each. It has quite an effect if you want to decode more than 1 instruction per cycle.
x86 has a stronger memory model than arm, which will come at an extra cost if implementing any sort of out-of-order execution. I'm not very familiar with how it affects the cache implementation.
The x86 instruction set is more complicated than arm, and instructions frequently decode into multiple uops. I believe that microcode is used more extensively in x86.