I'm curious why you think so (about the Z80, I mean). I seem to remember it being in very cheap computers as well (ZX Spectrum, doesn't get much cheaper than that) and was a great deal faster. I grew up with a 6502 and love it like a childhood pet but can't see how it 'ran rings' around the Z80.
In his talk http://www.youtube.com/watch?v=HW9AWBFH1sA#t=3m01s Michael Steil claimed that the 6502 had 60% fewer transistors than the Z80 but was twice as fast (in clock terms, I presume), while the Z80 had more registers and allowed slighly denser code.
I'll take a look at that, thanks. The typical Z80 had ran 4 times the clock rate at the 6502. Both CPUs had their pluses and minuses and I think for many practical purposes were roughly comparable. The design differences and choices are certainly interesting. I don't think the OP was right to claim the 6502 'ran rings' around the Z80 and that remains the case, after all the comments I got.
To somewhat counter that, the 6502 could read and write to the first 256 bytes of memory with shorter instructions. The 65816 expanded that idea to allow you to do that to any place in memory.
That's not the pattern I see when looking at the op-code/cycle chart. I recently implemented part of a C64-emulator in JavaScript and it seems very much like every step takes a cycle.
For example the instructions NOP(or CLI, STI, INX etc), 1 byte, 2 cycles. 1 cycle for fetching the instruction and one for executing the fetched instruction.
LDA addr,x seems to be pipelined a bit though. It's "AD lo hi" in memory and takes 4 cycles unless lo+x > 255, then it takes 5 cycles. The lo+x calculation seems to occur while hi is being read.
I will have to dig up my 6502 documentation, but, IIRC, by the time the processor executed the NOP (CLI, INX etc) it already fetched the next instruction, so, if it's another NOP, it will complete in one cycle instead of two. Unless you crossed a page boundary, which implies a one-cycle penalty.
Since I never wrote timing-critical code for the 6502 (apart from "make it as fast as possible") I cannot recall many specifics. Since you did, you certainly have a better understanding of how it worked.
I am restoring a 65c02-based //e clone, so, I may be able to properly measure instruction timings, but I won't hold my breath.
Yes you are right, the instruction timings were very exact as far as I remember. The only cases where there was an option was in the case of a branch taken or not.
I believe the 6502 could do things faster than the Z80. I once implemented the exact same program on a 6800 and a Z80. The 6800 is very close to the 6502. Speed wasn't an issue, but the Z80 version was noticeably bigger. And also felt more quirky to program.
The MSX 1 also had a hideous design flaw (for a gaming machine) that hid the framebuffer from the processor. IIRC, you had to do a couple IOs to get a single byte to or from the VRAM.
I remember the MSX2 had exactly the same flaw, it had a bigger video memory and some 2D acceleration primitives, but the access method was the same, through vpoke/vpeek.
